I. Papaefstathiou, D. Mprachos, C. Yannakou, N. Zervos, and D. Pnevmatikatos
SystemC, CPU, DSP, Network Processor
Current networking embedded systems are heavily heterogeneous environments involving hardware and software modules with complex communication among them. In order to prototype such systems in the most rapid manner, we need efficient methods for co-developing and, more importantly, co-simulating and co-verifying the hardware and the software modules. A very promising approach for such a development environment is the use of pure C++ for describing the system. In particular the software engineers can use C/C++ while the hardware design can be done in SystemC, a C++ class library capable of accurately modeling the hardware functionality. In this paper, we first present the efficiency of SystemC when designing Digital Signal Processors and networking CPU cores customized for media processing. We compare the design times and implementation characteristics of a 5-stage pipeline CPU core and a complicated DSP module when they are implemented in SystemC as opposed to a traditional hardware description language. Our results demonstrate that a networking and DSP processing unit can be implemented in about 40% less time in SystemC than in VHDL, while the silicon cost is used is no more than 20% higher; the performance of the hardware module is the same in both cases. Moreover, the SystemC hardware modules, communicate much faster with the software testbenches, which are commonly written in C, C++, therefore heavily accelerating the simulation time. As a result, we believe that SystemC is a very promising approach for designing prototypes of embedded systems in the most rapid way. In order to further accelerate the design process of embedded systems in general, We will release the demonstrated CPU and DSP cores as open-source, allowing anyone to use them.
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