Y. Ohmiya and H. Amano (Japan)
Multiprocessor simulation, Cache simulation, Binary translation
A dynamic binary-translation accelerator employed by an execution-driven simulator “ESPRIT/sim”, which mimics machine instructions and cache behavior of embedded multi-core systems, is proposed. Increasing number of multi-core in a chip, simulation of embedded system requires high performance. ESPRIT/sim minimizes dependency to simulated instruction set architectures and host instruction set architectures, and enlarges common parts of simulator to reduce developing costs of translators. ESPRIT/sim has flexible cache models written in C++, and dynamically translated execution code helps to reduce their overhead. Heterogeneous multiprocessors that become popular in embedded field can be simulated as well as homogeneous ones by using ESPRIT/sim. Here, we have evaluated SPLASH-2 simulation speed of multi processor systems up to 16 processors; then we have showed CPI as 6 through 10 for simulation and 11 through 23 for cache simulation. Similarly, ESPRIT/sim has simulated a heterogeneous multiprocessor system at high speed. For uni-processor systems, CINT95 programs have run from 2.6 to 9 CPI, and simulations with other statistics have been also boost up.
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