C. Gerousis (USA)
Single-electron transistor, nonlinear networks, and simula tion.
As semiconductor feature sizes shrink into the nanometer scale regime, device behavior becomes increasingly problematic leading eventually to the end of the roadmapf or scaling. Single-Electron Tunneling (SET) transistor iso ne of several nanoscale devices that have been suggestedt o overcome the problems accompanied by scaling. SETs offers attractive features such as small size and potentialt o operate with very low supply power, which suggestst hat these devices could be used in locally-connected cellular arrays ideal for signal and image processing applications. In this paper we present two single-electron architectures; the first consisting of the summing node inverter topology and the second architecture is based ont hreshold logic, which can accommodate both positivea nd negative weights. We demonstrate by way of MonteC arlo simulation two simple image processing applications, pixel shadowing and bit pattern detection.W e then discuss power consumption in SET arrays followed by conclusions.
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