J. Pang and G. Sutaria (USA)
FPGA, 2-D convolution, image processing, hardware resources, bandwidth
Two-dimensional (2-D) convolution is widely used in image processing applications. The full buffering (FB) and the partial buffering (PB) schemes reported in the previous work were used for 2-D convolution hardware design which had throughput of one convolution result per clock cycle. In this paper we describe the improved FB and PB architectures for 2-D convolution hardware design by using field programmable gate array (FPGA) device. We demonstrate that two convolution results can be calculated in one clock cycle when one extra row of pixel values is available and more multiplier circuits are added into the design. In order to reduce the hardware resource consumption, the 2-D convolution kernel coefficients can be multiplexed onto the multiplier input lines. We also provide a 3x3 2-D convolution design example and make comparisons on the FPGA design results using the proposed methods. The new schemes described in this paper are easy to implement in FPGA, and the obtained solution achieves the throughput of two convolution results per clock cycle.
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