C. Gerousis and A. Grepiotis (USA)
Single-electron device, digital circuits, simulation.
It is generally accepted that fundamental physicall imitations will ultimately hinder further feature sizer eduction in the conventional silicon transistor. Therefore,a lternative technologies will be necessary to allowc ontinued increase in the density of memory and logici nto the terabit regime. Among the emerging nanoelectronic technologies with greater scaling potential, is the Single-Electron Tunneling (SET) transistor, whiche xhibits its own periodic switching behavior, resulting in new paradigms for logic design and computation. This paper presents the design and simulation ofr econfigurable SET logic gates with control input. In such circuits bits of information are represented by thep resence or absence of single electrons at conducting islands. We first present the design of programmable logic gates and show the simulation results using a well known single-electron circuit simulator based on MonteC arlo technique. We then introduce a robust and efficient method of simulating combinational NAND arrays forB oolean function implementation using the SET circuits imulator. We finally end with conclusions and future nanotechnology prospects.
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