S. Jabeen and A. Tariq (Pakistan)
3-D DFT, 3-D DIF FFT, radix-2/4, radix-(2 × 2 × 2)/(4 × 4 × 4), 3-D image processing, hardware accelerator.
In this paper, we propose a hardware accelerator for com puting 3-D DFT. This architecture implements split radix 2/4 DIF FFT algorithm. The accelerator is a controller based architecture where the host processor moves the data to the local memory of the accelerator. The accelerator minimizes memory accesses, cost and critical path, and in creases efficiency of the processor. The architecture is de signed to be used in medical image processing applications like MRI.
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