An Efficient Intersection Algorithm Design of Ray Tracing for Many-Core Graphics Processors

K. Komatsu, Y. Kaeriyama, K. Suzuki, H. Takizawa, and H. Kobayashi (Japan)

Keywords

Ray Tracing, Intersection Algorithm, Compute Unified De vice Architecture (CUDA), ManyCore Processor Archi tecture

Abstract

Many-core processors have a vast potential to achieve inter active photo-realistic image synthesis by ray tracing. How ever, they need new efforts in program design to extract their performance. This paper proposes an architecture aware ray-triangle intersection test algorithm. As the ray triangle tests are the highest cost kernel in ray tracing, this paper explores an effective design and implementa tion of an intersection algorithm on a graphics processing unit (GPU) with many cores, and evaluates its performance through several experiments. Our intersection algorithm implementation can achieve the fast intersection tests by high-performance parallel processing on a many-core GPU with effective data management and load balancing. Ex perimental results show that our intersection algorithm on a 128-core GPU achieves 105 times faster intersection tests than that on a single-core processor. These results indicate that our intersection algorithm is promising in the coming era of many-core processors.

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