N. Ishihara and K. Abe (Japan)
DWT, signal processing, parallel architecture, efficient memory access, burst access, ASIC
The discrete wavelet transform (DWT) has been widely used for multimedia processing. The computationally de manding nature of DWT requires exploiting its parallelism. External memory is another concern in regards to improv ing the performance of two-dimensional DWT (2-DDWT). A novel 2-DDWT architecture which filters image data by utilizing as many data obtained by a DRAM burst access as possible is proposed. Simulation results revealed that the architecture reduces the number of clock cycles for DRAM memory accesses as well as the DRAM power consump tion with moderate cost of internal memory. Evaluation of the VLSI implementation of the architecture showed that the throughput of wavelet filtering was increased by par allelizing row filtering with a minimum area cost, thereby enabling DRAM full-page burst accesses to be exploited.
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