B.R. Gaster (UK)
overlays, memory contention, co-processors.
Due to the need to reduce power, size, and the requirement for real time access of both data and code, large caches have fallen out of favour for many embedded processors. Replaced by small software managed scrachpads a number of designs have been presented for managing the dynamic movement of data and/or code to and from larger, less re sponsive memories. To date these approaches have been deemed unnec essary in the context of memory contention. However this trend is changing with the introduction of highly parallel components as co-processors in SOC designs. While the same arguments concerning caches continue to be made in this context it is also the contention for bus and memory bandwidth that is seeing numerous levels of memory placed closer and closer to the core(s). Unlike the scratchpads seen thus far in the embedded domain often these memories can be hundreds of kilobytes and thus are capable of holding large working sets and in some cases even complete appli cations. In this paper we present an alternative approach to managing on-chip memory. A simple set of directives is provided, allowing the programmer to describe ’over lays’, themselves containing groupings of sub-routines, which are managed at runtime between on-chip and off chip memories.
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