S.R. Das (USA), J.F. Li, A. Hossain, A.R. Nayak, E.M. Petriu (Canada), and S. Biswas (USA)
Built-in self-test (BIST), embedded cores-based system on-chips (SOCs), fault injection, fault simulation, module under test (MUT), test pattern generator (TPG), Verilog HDL.
The complexity of modern digital circuits has increased enormously particularly due to paradigm shift from system-on-board to designs embracing embedded cores based system-on-chips (SOCs). The increased complexity has resulted in a huge challenge in setting up their appropriate fault testing environment. Though enormous efforts were directed to rapidly test very large-scale integrated (VLSI) circuit chips with reasonable cost, with advances in technology, new frontiers emerged. This paper aims at developing a method to verify and test circuit architecture under hardware and software co design environment, targeting specifically embedded cores-based system-on-chips (SOCs). The well-known concept of design-for-testability (DFT) is utilized in the paper based on the use of ModelSim simulation and verification tool to test simulate the entire design. Some partial results on ISCAS 85 combinational benchmark circuit are provided in the paper, besides a comparison of the results with some previous works.
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