R. Chandel, S. Sarkar, and R.P. Agarwal
Delay, interconnects, power dissipation, VLSI, voltage-scaled repeaters
This paper addresses various factors that determine delay and power dissipation of voltage-scaled optimal repeater-chain driven long interconnects. Using SPICE simulation extracted results, an analysis is presented. The analysis shows that by considerable voltage scaling, the number of repeater stages required for delay minimization can be reduced. This optimum number of repeaters depends on RLC load presented by the interconnect and repeater size. Lower RLC load has more influence on the optimum number of repeaters. In general, interconnect inductance reduces both delay and power dissipation. However, at extremely scaled voltages, inductive effect may increase power dissipation. Good delay and power management for voltage-scaled repeater loaded interconnect can be achieved through proper repeater sizing, voltage scaling, interconnect width optimization and interconnect material selection. Simulations show that the above results hold good irrespective of technology node.
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