Y.-s. L, L. Shen, Z.-y. Wang, and K. Dai
Simulation optimization, parallel simulation, CMP, architecture
Multi-core on one chip becomes the current main trend of micro processors’ architecture, and simulation plays an important role in evaluating new processor architectures. Traditional ways of sequential simulation for chip multiprocessor (CMP) require lots of simulation time which can’t be afford during processor design phase. Therefore, exploiting parallelism is necessary for speeding up the multi-core processor simulation. In this paper, we present a parallel CMP simulator, which is implemented by using POSIX threads, and also present the programming methodology for converting a sequential single core simulator to a parallel CMP simulator. Furthermore, the tradeoffs in parallel simulator implementation are also discussed. The experiments are carried out on a four-CPU dual core Xeon server. Under weak consistence order model, the parallel simulator achieves a speedup of 7.2X comparing with the sequential one.
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