J.-L. Olvera-Cervantes, J.-L. Medina-Monroy, R.-A. Chavez-Perez, A. Velazquez-Ventura (Mexico), and J.-A. Zamudio-Flores (Germany)
HJFETs, intrinsic transistor, small-signal extended equivalent circuit , transistor model
A new analytical method to determine the small-signal extended equivalent circuit model of Heterojunction Field Effect Transistors (HJFETs) is presented. The proposed extraction method is focused on a new analytical methodology for determining the extended intrinsic transistor elements Rfs Rfd and Rj. The proposed method differs from previous work in that differential resistances Rfs and Rfd are obtained from a new frequency dependent process based on simply analytical equations, which do not require assumptions in low frequencies or long optimization processes. The validity of this new extraction methodology is demonstrated by applying it to HJFETs transistors across the frequency range of 1 to 40 GHz. Fig. 1 Extended small-signal equivalent circuit model. The methodologies to determine the parasitic pad effects can be classified as: those based on special test structures and the based on forward and reverse bias measurements. In [1]-[8] different methods to remove parasitic-pad effects in FETs and HBTs have been proposed. Some methods using open/short test structures are presented in [2]-[5] while others based on [1] and [6]-[8].
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