A Timing-Driven Hybrid-Compression Algorithm for Faster Sum-of-Products

S. Das and S.P. Khatri (USA)


Combinational Synthesis, Datapath, Sum-of-Product, Par tial Product and Reduction Tree.


In state-of-the-art Digital Signal Processing (DSP) and Graphics applications, the arithmetic Sum-of-Product (SOP) is an important and computationally intensive oper ation, consuming a significant amount of delay. This paper presents a new architectural optimization approach to syn thesize a faster Sum-of-Product block, which can be very useful to reduce the delay in the critical path of the de sign. We have divided the problem of generating the Sum of-Product (SOP) into three parts: creation of the BitClus ters (sets of individual partial-product bits, which belong to the ith bitslice), hybrid compression-based reduction of the BitClusters and computation of the final sum result. Techniques used in all these three steps help to produce a faster implementation for the overall SOP block. Our ex perimental data shows that the SOP block generated by our algorithm is significantly faster (3.49% faster on average) than the corresponding block generated by a commercially available synthesis tool.

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