S. Das and S.P. Khatri (USA)
Combinational Synthesis, Datapath, Resource Sharing, Partial Product and Reduction Tree.
In the state-of-the-art digital designs, arithmetic blocks consume a major portion of the total area of the chip. Some of the most commonly used arithmetic operations are multiplication, multiply-accumulation (MAC), addition and subtraction. In this paper, we introduce a novel area efficient architecture, which can share multiplier, MAC, adder and subtractor blocks which are used in a mutually exclusive manner. In our algorithm, we transform each of the above-mentioned arithmetic operations to a subset of the MAC operation. We implement the core functions of the multiply-accumulation block only once and reuse different parts of the core sub-blocks for all four opera tions with the help of multiplexers. This architecture can be used in the non-timing critical paths (also called area critical paths) of the design, to save significant amount of area. Our experimental data shows that the proposed shared architecture results in about 35% area savings compared to the results obtained from a commercially available datapath synthesis tool.
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