S. Pampana, J.R. Heath, and A.V. Radun (USA)
Switched Reluctance Motors, Power Electronics, Digital Control, Digital Rotor Position Estimator, Prototype Testing, Validation.
Accurate Rotor position information is required to properly control phase currents in a manner to assure proper operation of Switched Reluctance Motors (SRMs). This manuscript addresses modeling and the use of Field Programmable Gate Array (FPGA) digital technology to implement a method to estimate the SRM’s rotor position using the inverse inductance value of the SRM’s phases. The estimated Rotor position is input to the Commutator circuit, also implemented in the FPGA, to determine when torque-producing currents should be input to the SRM phase windings. Digital Rotor Position Estimator and Commutator designs are described using the Verilog Hardware Description Language (HDL). The Estimator and Commutator designs are then implemented to a specific FPGA chip via use of an appropriate CAD tool-set. The digital Estimator and Commutator designs are first validated to be functionally correct via comparison of HDL simulation based virtual prototype models of the designs to comparative Simulink models of the Estimator and Commutator. The Estimator and Commutator designs, as implemented to the FPGA technology chip, were finally validated to be correct via experimental hardware prototype testing. Performance, of the non-optimized FPGA based SRM Rotor Position Estimator prototype, in terms of calculation time, was found to be 7 times that of a widely used commercial Digital Signal Processor (DSP) chip implementation of the same position estimator algorithm.
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