Y.-C. Jiang and Y.-T. Lai (Taiwan)
Reconfigurable computing, digital signal processing, computer-aided design, design automation.
A parallel processing reconfigurable architecture consists of multiple processor elements as FPGAs. Dynamically reconfigurable computing in the architecture combines with a parallel processing technique for high-level synthesis. A new partitioning algorithm is presented based on the architecture and needs to consider parallel processing different from transitional partitioning. The algorithm minimizes execution time to maximize application performance. A program or application is represented by a directed acyclic graph. In the algorithm a graph is divided into subgraphs by applying the greedy method and obtains the minimizing depth solution. Our algorithm efficiency and effectiveness is shown in the results.
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