C.-H. Kuo, C.-S. Chien, M.-F. Lin, and Y.-C. Tsai (Taiwan)
Clock generator, delay-locked loops (DLLs), frequency multiplier, programmable charging circuit (PCC), and fast-locking DLL
In this paper, a fast-locking delay-locked loop (DLL) based frequency multiplier for wide-range operation is proposed. A programmable charging circuit (PCC) to the loop filter is developed to accelerate the locking time of DLL. In the presented DLL, the pseudo-differential delay cell is adopted in the voltage-controlled delay line (VCDL) for the suppression of the common-mode noise. Five clock cycles of the least lock time can be reached in the presented DLL. A new DLL-based frequency multiplier with less active devices is also proposed to promote the operating frequency range from 200 MHz to 2.1 GHz. The simulated cycle-to-cycle jitter of the DLL is 31 ps at 320 MHz of the reference input. The prototype circuit has been fabricated in a 0.18 μm 1P6M CMOS technology. The core area excluding PADs is 0.36×0.37 mm2 . The power consumption of the proposed DLL is 24 mW from a 1.8 V of supply voltage.
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