C.-L. Yang and S.-K. Lu (Taiwan)
Memory, BIST, Repair, Reliability, Yield, BISR
A block-based redundancy architecture is proposed in this paper. The redundant rows/columns are divided into row /column blocks. Therefore, the repair of faulty memory cells can be performed at the row/column block level. Moreover, the redundant row/column blocks can be used to replace faulty cells anywhere in the memory array. This global characteristic is helpful for repairing cluster faults. The proposed redundancy architecture can be easily integrated with the embedded memory cores. Based on the proposed global redundant architecture, a heuristic MESP (modified essential spare pivoting) algorithm suitable for built-in implementation is proposed. According to experimental results, the area overhead for implementing the MESP algorithm is negligible. The repair rate is 99.94% for a 1M-bit (1024 × 1024-bit) SRAM.
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