C.-C. Kao, C.-C. Tzeng, and Y.-T. Lai (Taiwan)
System-on-Chip, interface synthesis, power, optimization, algorithm
Most of the Intellectual Properties (IPs) of the System on-Chip (SoC) are provided by different vendors such that they can have various characteristics. It makes that the interface circuit synthesis of the SoC is a time-consuming and error-prone design. In the past, some heuristic algorithms have been proposed for the interface circuit design of the System-on-Chip (SoC) but none of them can generate optimal solutions. The main contribution of this paper is to present an optimal interface synthesis algorithm for power optimization in interface circuit design of the SoC. Experiment results demonstrates the effectiveness of our algorithms.
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