A.H. Namin, H. Wu, and M. Ahmadi (Canada)
Multipliers, Finite Field, Binary Field, Redundant Repre sentation, Hardware, Elliptic Curve Cryptography
A high speed bit-serial word-parallel finite field multiplier using redundant basis is proposed. It has been shown that the proposed architecture has higher speed compared to the previously proposed hybrid architectures using the same basis while having moderate complexity. The hybrid archi tecture of the proposed design provides designer the ability to set the trade off between area and delay during the design process.
Important Links:
Go Back
