Design and Simulation for Three SEU Immune Latches in a 0.18µm CMOS Commercial Process

Y. Li, S. Yue, Y. Zhao, and G. Liang (PRC)


SEU, latch, sensitive node, layout


This paper reports three SEE (single event effect) immune latches designed in a 0.18µm CMOS commercial process, which are based on three memory cells having appeared in the recent years: HIT(Heavy Ion Tolerant cell), DICE(Dual Interlocked storage cell) and GDICE(DICE with guard-gates). An improvement for the later two latches drastically reduces static power consumption, decreases the number of transistors and enhances the SET (single event transient) immunity. Advantages and disadvantages of the three latches are enumerated apart. A simulation model for the SET on the sensitive node is proposed. It can be used for comparing the SEU (single event upset) immunity of the three latches. Some advices for layout design about SEE-hardening are provided. According to the simulation, it can be concluded that DICE latch and GDICE latch are less SEU-sensitive when only one sensitive node was stricken, but the HIT latch is less SEU sensitive when two nodes were stricken, if the special layout is regardless.

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