C. Liu, X. Qin, and X. Yan (PRC)
Parallel processing, EDO-SIMD, ISA, Media Processor
An Explicit Data Organization (EDO-SIMD) instruction set architecture (ISA) is proposed in this paper to reduce the data organization overhead of SIMD (Single Instruction Multiple Data) for media processors. It explicitly describes the data organization information in instruction words and merges the data organization with computation and store operation. An implementation of EDO-SIMD ISA based on a baseline SIMD processor is described and cycle accurate simulator for evaluation is designed. Simulation results show that, relative to the baseline SIMD architecture, EDO-SIMD ISA can achieve 1.34 to 1.40 speedups for the benchmark of real time H.264/AVC decoder and reduce 17.7% of the code size with only 0.49% increase in hardware area.
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