Steady State Noise Modeling in Computer Chips using Neural Networks

V. Nawale and T. Chen (USA)


Noise Modeling, Coupling Noise, Neural Networks, VLSI.


With continuing growth of computer technology, computer CPU chips are following the Moore’s Law for decades, re sulting in ever smaller geometry (currently at 65nm), and ever increasing complexity. One of the major issues in de signing computer chips is to estimate the steady state noise between driving sources. Excessive noise level at a given node in a circuit can cause logic failures. The conventional method to obtain the steady state noise level is through ta ble lookup where a large amount of lookup tables are gen erated. This method is simple but is tedious and requires a large amount of storage space. This paper proposes a new method of using neural networks to model the steady state noise level. The proposed method provides a simple and accurate method to determine steady state noise, and yet requires much less storage space.

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