P. Katta, M. Nourani, and R. Panigrahy (USA)
Computer Network Security, Pattern Matching, Site Secu rity Monitoring, String Matching
In this paper we present a hardware architecture for string matching. Our solutionbased on parallelized hashing is ca pable of handling wire line speeds with zero false-positive probability. String matching modules are extensively used in the network security domain especially in network intru sion detection systems where they are required to operate at wire line speeds. We analyze the performance of our architecture and show the expected throughput for various configurations of the system. We also report the details of our implementation in an Field Programmable Gate Ar ray (FPGA) and compare the performance of this system to an Application Specific Integrated Circuit (ASIC) imple mentation. Our analysis shows that our system is capable of matching ¢¤£¦¥§¥¦¥ strings at line speeds of ¨©¦ (i.e. £ "!$#%¢'& links).
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