A Programmable Instruction Decoder for Heterogeneous Multiprocessor Architectures

Y.-K. Jung (USA)


Heterogeneous computing, reconfigurable computing, extensible processors, digital signal processors, smart instruction decoder


A hardware/software co-reconfiguration technique is introduced to design a programmable instruction decoder for heterogeneous multiprocessor systems that do not employ programmable gate-array. This technique includes an off-chip static reconfiguration of heterogeneous multiple target instruction sets, followed by an on-chip dynamic reconfiguration of binary source instructions. This co reconfiguration technique does not require modifying existing compilers to retarget their new processors, nor does the technique oblige redesign of the processors to add new and/or extended instructions. This technique allows software developers to swiftly and accurately retarget their heterogeneous multiprocessor systems. In order to present the reconfiguration procedures and performance evaluations of the technique, a smart instruction decoder for Texas Instruments’ TMS320C55 digital signal processors and ARM’s ARM11 embedded processors was implemented and optimized.

Important Links:

Go Back