A Fast Latency Bound Estimation Algorithm for a Multithreaded Network Processor

H. Che, C. Kumar, and B. Menasinahal (USA)


Network Processor, Multithreaded Processor, Performance Analysis and testing, Network Protocols


How to allow fast network processor (NP) performance testing in supporting data path functions in a router is a challenging issue. It is more so in a router design phase when there are a vast number of design choices to be tested and the microcode for the data path functions is yet to be developed. In this paper, based on the Instruction-and LAtency-Budget-based NP analysis methodology (ILAB), we put forward an algorithm to allow NP processing element (PE) latency upper bounds to be estimated quickly (in a fraction of a second on a Pentium III PC). These performance bounds allow NP performance to be quickly tested solely based on a pseudo code for the data path functions. Case studies based on the code samples available in the Intel IXP 1200/2400 Developer Workbenches are performed. The performance bounds are found to be tight, within 17% of the cycle-accurate simulation results. With the algorithm proposed in this paper, ILAB can now be used as a powerful fast NP analysis methodology.

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