K. Appiah, P. Dickinson, and A. Hunter (UK)
FPGA, Baby-monitor, smart-camera, image segmentation
We have devised an automated visual surveillance system for monitoring sleeping infants. The system architecture requires that low-level image processing is executed on camera by an embedded signal processing unit: thus in tegrating more functionality into a single chip and realising lower product cost. The processing unit quantifies the level of scene activity using a specially designed background subtraction algorithm. In this paper we begin by describing the overall structure of our system. We proceed by present ing our algorithms, and demonstrating their effectiveness in measuring scene activity. We conclude by describing the FPGA-based low-level processing functions, and show how we have optimised them for maximum efficiency on this platform.
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