A. Méndez Patiño (Mexico), M.A. Martínez Peiró, F. Ballester, J.A. Canals, and J. Sifuentes (Spain)
ICT, DCT, H.264/AVC, FPGA, VLSI, Quantization.
This article presents a new architecture for 2-D ICT in H.264/AVC video standard oriented to FPGA. A sort of implementations are made in order to achieve optimal results for area and speed requirements. We describe forward and inverse 2D-ICT architecture proposal and the structure of the quantization module of both. Comparative results with other works referenced show the performance of our proposal in terms of gates, frequency and latency. These results over X. Spartan-3 present the best tradeoff vs the other proposals.
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