W. Wrona (Poland)
Simulation Tools, Hardware Acceleration, VHDL, IP Cores
In this paper we present the hardware accelerated VLSI simulator which can reduce verification time of soft IP. Acceleration of simulation is achieved due to a configurable FPGA module, which executes the most time consuming operations of a simulator. The results of comparison between the software and hardware time simulation confirm that the hardware simulator accelerates on all levels of HDL at a speed of 10-20 times that of a software workstation.
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