A 3.23 GOPS Parallel Architecture for Digital Image Pre-Processing

S. McBader (Italy) and P. Lee (UK)


Digital Signal Processing, Image PreProcessing, Parallel Architecture, Embedded Vision.


This paper presents a parallel architecture suitable for image pre-processing in embedded vision systems. The architecture integrates sixteen programmable processing elements, connected to an intelligent DMA channel and frame buffers. The processors are based on a 16-bit fixed point architecture, and have an instruction cycle time of 20ns when prototyped on a Xilinx FPGA. The architecture features a real-time processing capability realised by intelligent addressing and image-oriented data processing functions. The FPGA prototype of the architecture connects to a 256x256-pixel CMOS sensor, achieving 3.23 GOPS and up to 667 FPS of throughput at a clock frequency of 50 MHz. It is estimated to achieve a minimum of 6.46 GOPS and 1334 FPS at a clock frequency of 100 MHz when implemented in VLSI.

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