S.W. Chung, C.S. Jhon, and H.-S. Kim (Korea)
Cache replacement policy, Multiprocessor Systems, SMP node, Bus
In the SMP(Symmetric Multi- Processor), it is a general solution to connect the processors by the bus. However, even with small number of processors, the bus becomes a performance bottleneck. Thus it is important to reduce or distribute the bus traffic. In this paper, we propose the ef fective L2 cache replacement policy to distribute the bus traffic. When the victim block selected by the LRU cache replacement policy is modified, the other block that is not modified is replaced not to incur the writeback on the bus. The modified block, that is not replaced, would be first con sidered to be replaced at the next conflict/capacity miss. The proposed policy is shown to outperform the traditional LRU policy by up to 13.4 percent in the total execution time.
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