K. Jiang and Y. Sun (PRC)
array processors, time-space mapping, CAD.
Basing on the full-developed time-space mapping techniques of systolic array processor design, this paper focuses on transforming nested loops into systolic array processors, discusses different cases thoroughly, provides an efficient method to search the optimizing mapping matrixes by integer linear transformation and the features of objective functions. This paper only represents results for 2-dimentional systolic array implementations, but all of the results can be easily extended to systolic arrays with higher dimensions. A CAD software implementing this method has been developed.
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