M. Sowa, B.A. Abderazek, S. Shigeta, K. Nikolova, and T. Yoshinaga (Japan)
Parallel Queue Processor, Design, Queue Computing, Instruction Level Parallelism
In this paper, we propose a parallel Queue processor architecture (PQP) that uses Queue data structure for operands and results manipulations. The above architecture project, which started a couple of years ago here at Sowa laboratory, features simple pipeline, compact Queue based instruction set architecture, and is targeted for Internet applications and new class of terminals requiring small memory footprints and short programs run-times. The proposed architecture has been designed and then evaluated in software. First, we present the novel aspects of the above execution model as well as the principle underlying the architecture and the constraints that must be met. Second, to characterize the behavior of the proposed architecture, we present the preliminary evaluation results over a range of benchmark programs.
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