An Evaluation Architecture for a Network Coprocessor

J. Hatashita, J. Harris, H. Smith, and P.L. Nico (USA)


Network Interfaces, Network Performance, Reconfigurable Architecture, Network Coprocessor


This paper outlines research currently being conducted by the Cal Poly Intelligent Network Interface Card (CiNIC) project to develop a network coprocessor. The purpose of this coprocessor is to free the host machine from its net work processing duties as well as to allow for additional functionality such as hardware-based firewalling or quality of service (QoS) support. We provide an overview of the current CiNIC architecture as well as an introduction to and evaluation of the next generation CiNIC architecture. Our evaluation consisted of analyzing the performance and capabilities of an FPGA processor in order to determine whether it will meet our future development requirements. The FPGA’s performance was tested by timing the execution of the uClinux TCP/IP stack during send operations. The processor’s capabilities were tested by adding custom logic to the system and interfacing it with the uClinux operating system. We determined that both the performance and flexibility of the FPGA make it an ideal next generation CiNIC architecture.

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