H. Sato, and T. Yoshida (Japan)
compiler, loop unrolling, quantitative analysis, pipelining, data feeding cost, loop overhead reduction
Recently loop unrolling has been shed a new light from superscalar architectural point of view. In this paper, we quantitatively show that in addition to superscalar ef fect and scalar replacement effect, loop unrolling can hide memory latency, and that the combination of those effects improve the performance of loop unrolling. Moreover, we show that for out-of-order processors, loop unrolling just works as loop overhead reduction, where the old folklore has revived. A major contribution of this paper is that we analyze those effects using unrolling shapes that enables the symbolic and quantitative analysis, which has so far lit tle been tried unlike simple simulation-based analysis. Our analysis can make clear the behaviour of superscalar func tions and memory latency hiding in loop unrolling, and fur thermore interactions with out-of-order processors, which will give a new insight on compiler optimization and archi tecture research.
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