Towards a Unified Paradigm for Verification and Validation of Systems Engineering Design Models

L. Alawneh, M. Debbabi, F. Hassaïne, Y. Jarraya, P. Shahi, and A. Soeanu (Canada)


Systems Engineering, Verification and Validation, FormalVerification, Software Engineering Techniques.1.


We present a unified paradigm for verification and valida tion of software and systems engineering designs expressed in UML 2.0 or SysML. Our approach is based on an es tablished synergy between three salient approaches, which are model-checking, program analysis, and software engi neering techniques. To validate the proposed approach, we designed and implemented an automated environment, ca pable of assessing software and systems engineering design models. We provide a case study that shows our methodol ogy when applied to the verification of sequence diagrams and workflow systems modeled using activity diagrams.

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