S.R. Das (Canada, USA), D. Biswas, E.M. Petriu, M.H. Assaf (Canada), and M. Sahinoglu (USA)
Altera Max Plus II, built-in self-testing (BIST), embedded cores-based system-on-chip (SOC), sequential circuits, test access mechanism (TAM), test pattern generator (TPG), Verilog HDL, wrapper.
The evolution of the embedded cores-based design paradigm in recent times has created numerous challenging problems for the test design community. To develop suitable test environment and appropriate test methodologies for digital cores-based system-on-chip (SOC) is a fascinating area of research today. This paper attempts to develop viable solution options to these problems based on cores constructed from ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits. The wrapper that separates the core under test from other cores is assumed to be IEEE P1500-compliant. The cores and test access mechanism (TAM) are described in the paper using Verilog HDL, while TAM is implemented as a plain signal transport medium, being shared by all the cores in the SOC. The fault injection is done by a simulator that also generates the tests for the core. The fault simulation process is carried out after successful compilation of the cores, the individual core selection being done by the program running in the background.
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