A Layered Architecture for NOC Design Methodology

A. Agarwal and R. Shankar (USA)


Network on Chip, Modeling and Simulation, Quality of Service, System Level Design


Multiprocessor system on chip (MPSoC) platform is an innovative trend of System on Chip (SoC) that enhances system performance. Demanding quality of service parameters and performance metrics, especially in mobile applications, are leading to the exploration of even more innovative architectures for SoC. These will have to incorporate highly scalable, reusable, predictable, cost and energy efficient architectures. Network on Chip (NOC) is a key example of this trend. NOC separates computing and communication concerns in an elegant manner. We propose here a seven layered architecture for designing NOC-based systems. Such a platform can separate domain specific issues in separate layers, which will allow for more effective modeling of concurrency and synchronization issues, in an attempt to develop an optimized system. For such a layered architecture, models of computation (MOC) will provide a framework to model various algorithms and activities, while accounting for and exploiting concurrency and synchronization aspects. These MOCs may differ from one to another NOC region. Further, a combination of these MOCs may be needed to truly represent a given NOC region. We have analyzed various models of computation (MOC) suitable for NOC. MLDesigner provides a system level modeling platform which allows one to integrate such MOCs together. We present our efforts and experiences so far.

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