Design and Implementation of a VLIW Processor Simulation Environment with Instruction Scheduling Framework

A. Tsukikawa, F. Furukawa, T. Aoki, D. Oka, K. Ootsu, T. Yokota, and T. Baba (Japan)


VLIW, simulation, architecture simulator, instruction scheduling.


The advance of semiconductor technology is likely to make VLIW architecture popular due to its scalability and low power consumption. Therefore, detailed quantitative simulation systems for such next-generation VLIW proc essors are required. Now we are developing a simulation system for on-chip multi VLIW processors. CHA-MEN is an initial implementation of the system. Since instruction scheduling is an important factor of VLIW system, CHA-MEN provides integrated design of the simulator and language processor; that enables rapid evaluation of scheduling algorithm. CHA-MEN Scheduler Framework makes the swift implementation of scheduling algorithms easier. In this paper, we describe the design and implementa tion of CHA-MEN and demonstrate its practical benefits for scheduling experiment.

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