Dead Block Placement Avoidance in L1 Data Caches

A. Mahjur and A.H. Jahangir (Iran)


Superscalar Processors, L1 Data Cache, Cache Placement Algorithm


Three aspects of cache memories are important: hit ratio, access time, and power consumption. All of them depend on the cache size. A smaller cache not only has a smaller access time but also consumes less power. However, its hit ratio decreases as well. One approach to reduce the cache size, while preserving its hit ratio, is to increase its utilization, i.e. increase the number of times a data block services a processor request (use degree). This paper shows that the use degree of most data blocks is very low. After being fetched into the cache, around 20% of them are never used again, 20% of them are used once, and 20% of them are used three times. In addition, it shows that the use degree of a data block is highly predictable. Based on this information, we introduce several ways to condense the cache size while preserving its hit ratio.

Important Links:

Go Back