A Compact and Low-Power Implementation of the Montgomery Algorithm for a Public-Key Cryptosystem

J. Rejeb, C. Madaboosi, and T.T. Le (USA)

Keywords

Public key cryptography, RSA Algorithm, Modular exponentiation, Montgomery modular multiplication, LowPower consumption, FPGA implementation

Abstract

In this paper, we present a compact low-power RSA algorithm implementation. Speed and Area optimization in RSA's Modular Exponentiation block is achieved by using the Montgomery multiplication technique. We have designed the Montgomery scheme for a 768-bit key sized RSA algorithm and implemented using two Xilinx FPGA prototypes , Spartan 3s and Virtex 4. Spartan 3s occupies 6722 CLBs at 82 MHz; with a throughput of 40Mbps. Virtex 4 occupies 6974 CLBs at 161 MHz; with a throughput of 80 Mbps. We have estimated the power consumption using Xilinx X-Power tool. Spartan 3s and Virtex 4 consume a dynamic power of 1.148 W and 0.9 W respectively. We compare our results with previous implementations for speed, area, and power consumption and find out that our implementation has 40-50% reduction in power consumption.

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