Parametrical Characterization of Leakage Power in Embedded System Caches using Gated-VSS

D. Kudithipudi and E. John (USA)

Keywords

Cache Leakage, Gated Vss, Embedded Systems

Abstract

Rapid enhancement in embedded systems with a parallel evolution of nanotechnology design, statures significance to the study of leakage power consumption in these systems. Our work focuses on studying the characteristics of leakage power on cache structures for embedded systems. Using 70nm, 100nm, 130nm and 180nm technologies for analysis, we have applied gated-Vss, a leakage control technique to all simulations run by a modified HotLeakage [1]. The ratio of bitline leakage to the total loads and stores committed increased by two orders from 130nm to 70nm size. When the cache sizes were increased from 16k to 128k for L1, and 256k to 2M for L2, the dissipated leakage power of these systems showed a 50% increase.

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