S.R. Sappok, A. Neyer, and A. Kruth (Germany)
Calibration, Phase Locked Loop, Predistortion, Modula tion, DECT, Wireless
A novel calibration scheme for predistortion Σ∆ PLLs is proposed in this paper. In contrast to present calibration al gorithms this technique offers a digital representation of the high frequency phase characteristic. The architecture uses minimum chip area by synchronously sampling the data content of an asynchronous divider chain. Using this tech nique to detect the phase difference during a step response allows to determine the real loop gain within 7 µs with an accuracy better than 0.1%. Obtaining this, the deviation from the desired loop gain can be adjusted by a digitally controlled charge pump in order to derive the wanted loop transfer function. This is mandatory for predistortion mod ulation loops. The architecture is designed by systemthe oretical calculation of the loop behaviour and verified by mixed signal VHDL-AMS simulations.
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