VLSI Design of a Very Low Bit Rate Speech Decoder

J.-C. Wang, J.-F. Wang, Y.-F. Chao, and M.-C. Shi (Taiwan)

Keywords

ASIC, speech coding, LPC, LSP, VLSI, vocoder.

Abstract

This study presents an FBLPC vocoder and an ASIC architecture for its decoding process. The FBLPC vocoder is based a forward-backward waveform prediction, and the required bit rate is approximately 1.2 kbps. Regarding the ASIC decoder, dedicated architectures are devised for the separate decoding modules. These architectures are then integrated through resource-sharing to achieve a cost effective design.

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• DOI:
• From Proceeding (493) Circuits, Signals, and Systems - 2005

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