F. Menichelli, M. Olivieri, S. Smorfa, and I. Zaccardini (Italy)
Image processing, Jpeg2000, software optimization, VLIW architecture, data-cache optimization, Systems-on Chips.
This work describes the optimization of a Jpeg2000 encoder implementation on an embedded VLIW CPU core. We demonstrate that specifically designed source code leads to significant performance improvements by carefully exploiting the hardware resources of the underlying processor architecture. Conversely, we show that the generic Jpeg2000 source code yields performance results comparable with those obtained on a single-issue RISC CPU (ARM). The dedicated algorithm implementation, with over 40% savings in the total clock cycle count, demonstrates the effectiveness of VLIW CPU cores in high-performance, low-cost and low-power embedded computing platform.
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