Modelling and Simulation of Off-Chip Communication Architectures for High-Speed Packet Processors

J. Engel, D. Lacks, and T. Kocak (USA)


Network processor, k-ary n-cube networks, off-chip inter connects, simulation framework, line-card design, worm hole routing


In this work, we propose an event-driven, custom-designed interconnect simulation environment to evaluate the perfor mance of packet-based off-chip k-ary n-cube interconnect architectures for line cards. The simulator uses the state of-the-art software design techniques to provide the user with a flexible yet robust tool, that can emulate multiple in terconnect architectures under non-uniform traffic patterns. Moreover, the simulator offers the user with full control over network parameters, performance enhancing features and simulation time frames that make the platform as iden tical as possible to the real line card physical and functional properties. The k-ary n-cube architectures allow multiple packet processing elements on a line card to access multiple memory modules. In addition, they can sustain current line rates and higher, while distributing the load among multi ple memories. The objective of the proposed simulator is to compare among different off-chip interconnect architec tures for network line cards and determine which intercon nect can significantly increase the memory bandwidth and the overall system throughput.

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