Z. Lin, H. Yang, L. Zhong, J. Sun, and S. Xia (PRC)
Analog-to-digital converter, CMOS process tolerance analysis, modelling and simulation, computer-aided design, Monte Carlo statistical analysis
For CR SAR ADC to be embedded in a SOC (System on-Chip), it becomes necessary to acquire how an underlying digital CMOS process that is used to implement the SOC would limit the performance of the ADC that contains key analog components such as the capacitor array. In this paper, impact of the capacitor array mismatch on the attainable resolution of the CR SAR ADC is analysed and modeled in closed form expressions. The proposed model offers possible design trade-off among various factors including appropriate selection of the capacitor array size, the CMOS process parameters, the layout structures, etc. and hence facilitates the co-design between the analog and digital circuits. The model is verified with MATLAB as well as Monte Carlo statistical simulations. The results give some important insight into the tolerance behavior of the CR SAR ADC, which may form a theoretical basis for further design optimization.
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