A Novel Deep Submicron Low Power Bus Coding Technique

K.S. Sainarayanan, J.V.R. Ravindra, and M.B. Srinivas (India)


Bus, Coupling Transition, Self Transition, Low Power, DSM


With shrinking feature size, increasing frequency and chip density, power dissipation on data bus has become the most predominant factor than the power dissipation in other parts of the circuitry. Further de facto, the inter-wire capacitance has become the dominating factor in Deep Submicron Technology (DSM) compared to substrate capacitance. So, the earlier schemes of minimizing the substrate capacitances are not valid in these buses. By taking these facts into account a novel bus coding technique is proposed in this paper which reduces the inter-wire capacitance by 14% for 8, 16 and 32 bit bus compared to unencoded bus. The proposed method divides the bus lines into two groups and selects that grouping which yields the minimum inter-wire capacitance.

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