A. Yamawaki and M. Iwane (Japan)
SOC–multiprocessor, Cache memory, Communication, Conditional synchronization, Mutual exclusion, Barrier
A SOC–multiprocessor can achieve a high performance by using many parallel processing technologies. On a shared memory multiprocessor, synchronization and communica tion are performed through shared variables. In general, synchronization is performed apart from communication. On a SOC–multiprocessor, the TSVM cache combines communication and synchronization with the coherence maintenance among the processor cores. That is, one co herence transaction through a high–speed inter–connection on the chip realizes the communication and synchroniza tion via a shared variable. This paper introduces the several instructions of which each instruction has the individual co herence maintenance scheme to the TSVM cache. By com bining these instructions, you can realize the efficient com munication and synchronization primitives easily and sys tematically, which are useful in a parallel processing gen erally. We perform the experiments of the primitives and the applications using them on a clock–accurate simulator written in VHDL. The result shows that the TSVM cache can improve a performance of 8.5 times compared with a traditional cache memory. It is also confirmed that although the load instruction not changing the synchronization state does not achieve the best performance, it can reduce a bus traffic of 40% on an application program.
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